Staff ASIC Design Engineer

Due to growth, this is a fantastic opportunity to join a global company in their Cambridge office. The role offers broad ownership across the entire ASIC development cycle, from architecture and RTL design through verification, DFT, implementation, and silicon validation. The role combines challenging mixed-signal design work with the opportunity to provide technical leadership and contribute to design methodology improvements in one of the UK’s leading technology and Semiconductor hubs.
Key responsibilities
Design and develop functional digital blocks and contribute to the delivery of complete mixed-signal ASICs from concept through to full production maturity
Support product definition activities through feasibility studies, architecture development, and FPGA-based digital emulation
Develop RTL designs in SystemVerilog that meet system performance, functionality, and quality requirements
Create comprehensive block-level verification environments and testbenches to validate digital functionality
Perform digital synthesis and develop appropriate physical design constraints to achieve power, performance, and area (PPA) targets
Generate and maintain high-quality design documentation and actively participate in design reviews
Provide technical leadership and mentorship to other team members
Drive continuous improvement of digital design methodologies and best practices
Skills and expertise
Have a minimum of 5 years' experience in digital IC design using standard-cell methodologies
Possess deep knowledge of industry-standard digital design methodologies and best practices
Demonstrate expertise in fully synthesised digital design flows, including RTL development and logic synthesis
Be highly proficient in SystemVerilog and modern digital EDA toolchains
Have experience applying timing and physical design constraints within automted place-and-route flows
Understand production test requirements and have hands-on experience implementing DFT techniques such as scan-based testing to maximise test coverage
Have practical experience with low-power digital design techniques and power optimisation methodologies
Be proficient in scripting languages such as TCL and Python
Benefits
A competitive compensation and benefits package is offered, including joining stock + Employee stock purchase scheme and a base salary.
Please contact Rachel Mason for more information.