Senior Verification Engineer - FPGA/ASIC & Open-Source Tools

Hudson River Trading (HRT) seeks experienced Design Verification engineers to write testbenches and verification environments for high-performance FPGA/ASIC hardware. You will contribute to verification plans, root-cause RTL bugs, and collaborate closely with designers in a fast-paced, real-time trading environment.

Preferred candidates have 2+ years in RTL verification, strong SystemVerilog/UVM skills, and experience with Python. Familiarity with Verilator/Cocotb and Linux is a plus.