Senior Subsystem Design Engineer (RTL/IP)

Arm is seeking a Staff Subsystem Design Engineer to lead RTL design and integration of complex IPs and compute subsystems. You will specify, architect, and implement subsystems while collaborating with architecture, verification, and implementation teams to achieve robust designs.

We value deep expertise in SystemVerilog, AMBA protocols, and power/clock strategies, with a track record of delivering high-quality IP in a challenging environment. Hybrid working arrangements apply within the UK.