Fpga Design Engineer

Senior FPGA RTL Engineer Location: Cambridge (Flexible/Hybrid) Salary: £150k+ bonus My client is an innovative technology company developing cutting-edge, high-performance systems for demanding real-time applications. As part of continued growth and investment in next-generation platforms, they are seeking an experienced Senior FPGA RTL Engineer to join their engineering team. This is an excellent opportunity to work on technically challenging projects where performance, reliability and optimisation are critical. You'll play a key role in shaping future FPGA architectures and mentoring engineers within a highly skilled development environment. The Role As a Senior FPGA RTL Engineer, you will take ownership of FPGA development projects from architecture through to implementation and verification. Working closely with multidisciplinary engineering teams, you will help drive innovation and contribute to the development of next-generation hardware platforms. Key responsibilities include: * Designing and developing advanced FPGA architectures and RTL solutions * Defining micro-architectures for high-performance digital systems * Implementing RTL designs using SystemVerilog * Developing comprehensive test benches and verification environments * Performing simulation, synthesis, place and route, timing closure and hardware validation * Optimising designs for performance, resource utilisation and reliability * Supporting and mentoring FPGA engineers within the team * Collaborating with engineering leadership to align technical roadmaps with business objectives * Working closely with software, hardware and systems engineers throughout the development lifecycle * Contributing to the continuous improvement of FPGA design methodologies and processes Requirements * 7+ years of FPGA/RTL design experience * Strong expertise in RTL development using SystemVerilog * Proven experience delivering complex FPGA-based systems * Experience using FPGA development tools such as Xilinx Vivado, Intel Quartus or equivalent * Strong understanding of FPGA architecture, timing analysis and optimisation techniques * Experience with simulation, synthesis and verification methodologies If you're interested, please apply below