Senior RTL CPU Architect – RISC‑V/Chisel

SiFive

Screened

Cambridge

Posted 2 weeks ago

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About the role

SiFive in Cambridge is looking for a CPU Microarchitecture/RTL design engineer to join their innovative team, focusing on RISC-V architecture design. Candidates should have a BS/MS degree and at least 3 years of relevant design experience, particularly in CPU RTL.

The role involves working on new hardware IP solutions in a fast-paced environment, emphasizing quality and teamwork. A strong background in hardware design languages and software engineering is essential.

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